AMIS-49587 Datasheet, PDF (17/59 Pages) ON Semiconductor – Power Line Carrier Modem

AMIS−49587
CLOCK AND CONTROL
Oscillator
The oscillator works with a standard parallel resonance
crystal of 24 MHz. XIN is the input to the oscillator inverter
gain stage and XOUT is the output.
XTAL _IN
XTAL _ OUT
24 MHz
CX
RX
CX
V _SSA
V _SSA
Figure 12. Placement of the Capacitors and Crystal with Clock Signal Generated Internally
For correct functioning the external circuit illustrated in
Figure 12 must be connected to the oscillator pins. For a
crystal requiring a parallel capacitance of 20 pF C_X must be
around 30 pF. (Values of capacitors are indicative only and
are given by the crystal manufacturer). To guarantee startup
the series loss resistance of the crystal must be smaller than
80 W.
A parallel resistor R_X = 1 MW is recommended to improve
the clock symmetry.
Zero Crossing Detector
M50HZ_IN is the mains frequency analog input pin − 50
or 60 Hz. This pin is used to detect the crossing of the zero
voltage on one selected phase. This information is used,
after filtering with the internal PLL, to synchronize frames
with the mains frequency. In case of direct connection to the
mains, the use of a series resistor of 1 MW is advised in order
to limit the current flowing through the external protection
diodes. The zero crossing detector output is logic zero when
the input is lower than the falling threshold level and a logic
one when the input is higher than the rising threshold level.
The falling edges of the output of the zero crossing detector
are filtered by a period between 0.5 ms and 1 ms. Rising
edges are not filtered.
COMMUNICATION CONTROLLER
Serial Communication Interface (SCI)
The SCI allows asynchronous communication. It can
communicate with a UART = Universal Asynchronous
Receiver Transmitter, ACIA = Asynchronous
Communication Interface Adapter and all other chips that
employ standard asynchronous serial communication. The
serial communication interface allows only half duplex
communication.
IDLE (mark)
LSB
MSB
IDLE (mark)
Start D0 D1 D2 D3 D4 D5 D6 D7 Stop
t_BIT
8 data bits
t_BIT
1 character
Figure 13. Data Format
The transmitting has the following characteristics:
♦ Half duplex.
♦ Standard NRZ format.
♦ Start bit, 8 data bits and 1 stop bit.
♦ Hardware programmable baud−rate (4800, 9600,
19200 and 38400 baud).
♦ 0−5 V levels with open drain for TxD.
♦ 0−5 V levels for RxD and T_REQ.
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