V850E1 Datasheet, PDF (98/226 Pages) NEC – 32-Bit Microprocessor Core

CHAPTER 5 INSTRUCTIONS
<Multiply instruction>
MULU
Multiply word by register/immediate (9-bit)
Multiply Word Unsigned
Instruction format (1) MULU reg1, reg2, reg3
(2) MULU imm9, reg2, reg3
Operation
(1) GR [reg3] || GR [reg2] ← GR [reg2] × GR [reg1]
(2) GR [reg3] || GR [reg2] ← GR [reg2] × zero-extend (imm9)
Format
Opcode
(1) Format XI
(2) Format XII
15
0 31
16
(1) rrrrr111111RRRRR wwwww01000100010
15
0 31
16
(2) rrrrr111111iiiii wwwww01001IIII10
iiiii is the lower 5 bits of 9-bit immediate data.
IIII is the higher 4 bits of 9-bit immediate data.
Flag
CY –
OV –
S
–
Z
–
SAT –
Explanation
(1) Multiplies the word data of general-purpose register reg2 by the word data of general-
purpose register reg1, and stores the higher 32 bits of the result (64-bit data) in general-
purpose register reg3 and the lower 32 bits in general-purpose register reg2. The data of
general-purpose register reg1 is not affected.
(2) Multiplies the word data of general-purpose register reg2 by a 9-bit immediate data, sign-
extended to word length, and stores the higher 32 bits of the result (64-bit data) in general-
purpose registers reg3 and the lower 32 bits in general-purpose register reg2.
Remark
If the address of reg2 is the same as the address of reg3, the higher 32 bits of the result are
stored in reg2 (= reg3).
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User’s Manual U14559EJ3V1UM