V850E1 Datasheet, PDF (134/226 Pages) NEC – 32-Bit Microprocessor Core

CHAPTER 5 INSTRUCTIONS
<Store instruction>
ST.H
Store halfword
Store
Instruction format ST.H reg2, disp16 [reg1]
Operation
adr ← GR [reg1] + sign-extend (disp16)
Store-memory (adr, GR [reg2], Halfword)
Format
Opcode
Format VII
15
0 31
16
rrrrr111011RRRRR ddddddddddddddd0
ddddddddddddddd is the higher 15 bits of disp16.
Flag
CY –
OV –
S–
Z–
SAT –
Explanation
Adds 16-bit displacement, sign-extended to word length, to the data of general-purpose
register reg1 to generate a 32-bit address, and stores the lower halfword data of general-
purpose register reg2 in the generated address.
Caution
The result of adding the data of general-purpose register reg1 and the 16-bit displacement
sign-extended to word length can be of two types depending on the type of data to be
accessed (halfword, word), and the misalign mode setting.
• Lower bits are masked by 0 and address is generated (when misaligned access is
disabled)
• Lower bits are not masked and address is generated (when misaligned access is
enabled)
(when misaligned access is enabled in type D, E, and F products)
For details on misaligned access, see 3.3 Data Alignment.
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User’s Manual U14559EJ3V1UM