V850E1 Datasheet, PDF(193/226 Page) NEC – 32-Bit Microprocessor Core

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V850E1 Datasheet, PDF (193/226 Pages) NEC – 32-Bit Microprocessor Core

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CHAPTER 9 SHIFTING TO DEBUG MODE

Figure 9-1. Single-Step Operation Execution Flow

User mode

DBTRAP instruction execution

Debug mode

Single-step

operation setting

1 instruction executed

DBPC â Restored PC

DBPSW â PSW

PSW.NP â 1

PSW.EP â 1

PSW.ID â 1

PC

â 00000060H

DIR.SE

â1

DBPSW [11] â 1

DBPC

â Restored PC

DBRET instruction execution

1 instruction executed

DBPC â Restored PC

DBPSW â PSW

PSW.NP â 1

PSW.EP â 1

PSW.ID â 1

PC

â 00000060H

Debug monitor routine

.

..

Single-step

operation clearing

Debug monitor routine

DBPSW [11] â 0

DIR.SE

â0

DBRET instruction execution

1 instruction executed

1 instruction executed

Remark

The SS flag of the PSW is automatically cleared to 0 when an interrupt request is generated in user

mode in a single-step operation. Therefore, the single-step operation is not performed in the interrupt

servicing routine (the SS flag is set to 1 again due to the restore processing from the interrupt

servicing routine (EIPSW â PSW)).

The processing flow may vary depending on the instruction that is executed when an interrupt occurs

(see Figure 9-2).

Userâs Manual U14559EJ3V1UM

193

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