V850E1 Datasheet, PDF (225/226 Pages) NEC – 32-Bit Microprocessor Core

APPENDIX G REVISION HISTORY
G.2 History of Revisions up to This Edition
A history of the revisions up to this edition is shown below. “Applied to:” indicates the chapters to which the revision
was applied.
Edition
Major Revision from Previous Edition
2nd _{• Addition of following products (under development) to target products}
NB85ET, NU85E, NU85ET, µPD703108, 703114, 70F3114, 703116
• Deletion of following product from target products
µPD703117
• Change of following products from “under development” to “developed”
µPD703106, 703107, 70F3107
Change of Note in Figure 2-1 Registers
Change of Table 2-2 System Register Numbers
(1/2)
Applied to:
Throughout
CHAPTER 2
REGISTER SET
Addition of Note to Figure 2-6 Program Status Word (PSW)
Addition of Note to 2.2.6 Exception/debug trap status saving registers (DBPC, DBPSW)
Change of Caution in 2.2.8 Debug interface register (DIR)
Change of Caution in 2.2.9 Breakpoint control registers 0 and 1 (BPC0, BPC1)
Change of Figure 2-11 Breakpoint Control Registers 0 and 1 (BPC0, BPC1)
Change of Caution in 2.2.10 Program ID register (ASID)
Change of Caution in 2.2.11 Breakpoint address setting registers 0 and 1 (BPAV0, BPAV1)
Change of Caution in 2.2.12 Breakpoint address mask registers 0 and 1 (BPAM0, BPAM1)
Change of Caution in 2.2.13 Breakpoint data setting registers 0 and 1 (BPDV0, BPDV1)
Change of Caution in 2.2.14 Breakpoint data mask registers 0 and 1 (BPDM0, BPDM1)
Addition of Caution to 5.2 (10) Debug function instructions
Addition of Caution to DBRET in 5.3 Instruction Set
CHAPTER 5
INSTRUCTION
Addition of Caution to DBTRAP in 5.3 Instruction Set
Change and addition of Note in Table 5-6 List of Number of Instruction Execution Clock
Cycles (NB85E, NB85ET, NU85E, and NU85ET)
Change of Note in Table 5-7 List of Number of Instruction Execution Clock Cycles
(V850E/MA1, V850E/MA2, V850E/IA1, and V850E/IA2)
Addition of Note to Table 6-1 Interrupt/Exception Codes
Addition of Caution to 6.2.3 Debug trap
CHAPTER 6
INTERRUPT AND
EXCEPTION
Addition of Remark and Example to 8.1.2 2-clock branch
Addition of Caution to 8.1.3 Efficient pipeline processing
CHAPTER 8
PIPELINE
Correction of description in 8.2 (2) V850E/MA1, V850E/MA2, V850E/IA1, V850E/IA2
Correction of description in 8.2.1 (2) SLD instructions
Correction of description in 8.2.3 Multiply instructions
Addition of Remark to 8.2.4 (3) Divide instructions
Correction of description in 8.2.8 (2) TST1 instruction
Addition of Remark to 8.2.9 (3) DI, EI instructions
Addition of Caution to 8.2.9 (7) NOP instruction
User’s Manual U14559EJ3V1UM
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