V850E1 Datasheet, PDF (82/226 Pages) NEC – 32-Bit Microprocessor Core

CHAPTER 5 INSTRUCTIONS
<Load instruction>
LD.B
Load byte
Load
Instruction format LD.B disp16 [reg1], reg2
Operation
adr ← GR [reg1] + sign-extend (disp16)
GR [reg2] ← sign-extend (Load-memory (adr, Byte))
Format
Opcode
Format VII
15
0 31
16
rrrrr111000RRRRR dddddddddddddddd
Flag
CY –
OV –
S
–
Z
–
SAT –
Explanation
Adds the data of general-purpose register reg1 to a 16-bit displacement sign-extended to word
length to generate a 32-bit address. Byte data is read from the generated address, sign-
extended to word length, and stored in general-purpose register reg2.
Remark
If an interrupt occurs during instruction execution, execution is aborted, and the interrupt is
serviced. Upon returning from the interrupt, the execution is restarted from the beginning, with
the return address being the address of this instruction.
[For type D, E, and F products]
Depending on the resource to be accessed (internal ROM, internal RAM, on-chip peripheral
I/O, external memory), the bus cycle may be switched (this will not occur if the same resource
is accessed).
[For type A, B, and C products]
The bus cycle sequence for accessing the different resources connected to each bus (VFB,
VDB, VSB, NPB, instruction cache bus, data cache bus) may be switched (this will not occur if
the same bus is accessed).
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User’s Manual U14559EJ3V1UM