V850E1 Datasheet, PDF (153/226 Pages) NEC – 32-Bit Microprocessor Core

CHAPTER 5 INSTRUCTIONS
Table 5-6. List of Number of Instruction Execution Clock Cycles (3/3)
Type of
Instruction
Branch
instructions
Mnemonic
Bcond
JARL
JMP
JR
Bit manipulation
instructions
CLR1
CLR1
NOT1
NOT1
SET1
SET1
TST1
TST1
Special
instructions
CALLT
CTRET
DI
DISPOSE
DISPOSE
EI
HALT
LDSR
NOP
PREPARE
PREPARE
PREPARE
PREPARE
RETI
STSR
SWITCH
TRAP
Debug function
instructions^{Note 8}
DBRET
DBTRAP
Undefined instruction code
Operand
Byte
disp9 (When condition is satisfied) 2
disp9 (When condition is not
2
satisfied)
disp22, reg2
4
[reg1]
2
disp22
4
bit#3, disp16 [reg1]
4
reg2, [reg1]
4
bit#3, disp16 [reg1]
4
reg2, [reg1]
4
bit#3, disp16 [reg1]
4
reg2, [reg1]
4
bit#3, disp16 [reg1]
4
reg2, [reg1]
4
imm6
2
–
4
–
4
imm5, list12
4
imm5, list12, [reg1]
4
–
4
–
4
reg2, regID
4
–
2
list12, imm5
4
list12, imm5, sp
4
list12, imm5, imm16
6
list12, imm5, imm32
8
–
4
regID, reg2
4
reg1
2
vector
4
–
4
–
2
4
Number of Execution Clocks
i
2^{Note 4}
1
r
2^{Note 4}
1
l
2^{Note 4}
1
2^{Note 5}
3^{Note 5}
2^{Note 5}
3^{Note 6}
3^{Note 6}
3^{Note 6}
3^{Note 6}
3^{Note 6}
3^{Note 6}
3^{Note 6}
3^{Note 6}
4^{Note 5}
3^{Note 5}
1
n+1^{Note 7}
n+3^{Note 7}
1
1
1
1
n+1^{Note 7}
n+2^{Note 7}
n+2^{Note 7}
n+3^{Note 7}
3^{Note 5}
1
5
3^{Note 5}
3^{Note 5}
3^{Note 5}
3
2^{Note 5}
3^{Note 5}
2^{Note 5}
3^{Note 6}
3^{Note 6}
3^{Note 6}
3^{Note 6}
3^{Note 6}
3^{Note 6}
3^{Note 6}
3^{Note 6}
4^{Note 5}
3^{Note 5}
1
n+1^{Note 7}
n+3^{Note 7}
1
1
1
1
n+1^{Note 7}
n+2^{Note 7}
n+2^{Note 7}
n+3^{Note 7}
3^{Note 5}
1
5
3^{Note 5}
3^{Note 5}
3^{Note 5}
3
2^{Note 5}
3^{Note 5}
2^{Note 5}
3^{Note 6}
3^{Note 6}
3^{Note 6}
3^{Note 6}
3^{Note 6}
3^{Note 6}
3^{Note 6}
3^{Note 6}
4^{Note 5}
3^{Note 5}
1
n+1^{Note 7}
n+3^{Note 7}
1
1
1
1
n+1^{Note 7}
n+2^{Note 7}
n+2^{Note 7}
n+3^{Note 7}
3^{Note 5}
1
5
3^{Note 5}
3^{Note 5}
3^{Note 5}
3
User’s Manual U14559EJ3V1UM
153