V850E1 Datasheet, PDF (202/226 Pages) NEC – 32-Bit Microprocessor Core

APPENDIX B INSTRUCTION LIST
Table B-1. Instruction Function List (in Alphabetical Order) (5/11)
Mnemonic
Operand
Format
MOVHI
imm16, reg1, reg2
VI
MUL
MUL
reg1, reg2, reg3
XI
imm9, reg2, reg3
XII
MULH
reg1, reg2
I
MULH
imm5, reg2
II
MULHI
imm16, reg1, reg2
VI
MULU
reg1, reg2, reg3
XI
MULU
imm9, reg2, reg3
XII
NOP
(None)
I
NOT
reg1, reg2
I
NOT1
bit#3, disp16 [reg1]
VIII
NOT1
reg2, [reg1]
IX
Flag
Instruction Function
CY OV S Z SAT
−
−
−
−
− Move High Halfword. Adds word data, in which
the higher 16 bits are defined by the 16-bit
immediate data while the lower 16 bits are set
to 0, to the word data of reg1 and stores the
result in reg2.
−
−
−
−
− Multiply Word. Multiplies the word data of reg2
by the word data of reg1, and stores the result
in reg2 and reg3.
−
−
−
−
− Multiply Word. Multiplies the word data of reg2
by the 9-bit immediate data sign-extended to
word length, and stores the result in reg2 and
reg3.
−
−
−
−
− Multiply Halfword. Multiplies the lower halfword
data of reg2 by the lower halfword data of
reg1, and stores the result in reg2 as word
data.
−
−
−
−
− Multiply Halfword. Multiplies the lower halfword
data of reg2 by a 5-bit immediate data, sign-
extended to halfword length, and stores the
result in reg2 as word data.
−
−
−
−
− Multiply Halfword Immediate. Multiplies the
lower halfword data of reg1 by a 16-bit
immediate data, and stores the result in reg2.
−
−
−
−
− Multiply Word Unsigned. Multiplies the word
data of reg2 by the word data of reg1, and
stores the result in reg2 and reg3.
−
−
−
−
− Multiply Word Unsigned. Multiplies the word
data of reg2 by the 9-bit immediate data sign-
extended to word length, and store the result
in reg2 and reg3.
−
−
−
−
− No Operation.
−
0 0/1 0/1
− Not. Logically negates (takes 1’s complement
of) the word data of reg1, and stores the result
in reg2.
−
−
− 0/1 − Not Bit. First, adds the data of reg1 to a 16-bit
displacement, sign-extended to word length, to
generate a 32-bit address. The bit specified by
the 3-bit bit number is inverted at the byte data
location referenced by the generated address.
−
−
− 0/1 − Not Bit. First, reads reg1 to generate a 32-bit
address. The bit specified by the lower 3 bits
of reg2 of the byte data of the generated
address is inverted.
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