V850E1 Datasheet, PDF (122/226 Pages) NEC – 32-Bit Microprocessor Core

CHAPTER 5 INSTRUCTIONS
<Load instruction>
SLD.H
Short format load halfword
Load
Instruction format SLD.H disp8 [ep], reg2
Operation
adr ← ep + zero-extend (disp8)
GR [reg2] ← sign-extend (Load-memory (adr, Halfword))
Format
Opcode
Format IV
15
0
rrrrr1000ddddddd
ddddddd is the higher 7 bits of disp8.
Flag
CY –
OV –
S
–
Z
–
SAT –
Explanation
Adds 8-bit displacement, zero-extended to word length, to the element pointer to generate a
32-bit address. Halfword data is read from the generated address, sign-extended to word
length, and stored in reg2.
Remark
If an interrupt occurs during instruction execution, execution is aborted, and the interrupt is
serviced. Upon returning from the interrupt, the execution is restarted from the beginning, with
the return address being the address of this instruction.
[For type D, E, and F products]
Depending on the resource to be accessed (internal ROM, internal RAM, on-chip peripheral
I/O, external memory), the bus cycle may be switched (this will not occur if the same resource
is accessed).
[For type A, B, and C products]
The bus cycle sequence for accessing the different resources connected to each bus (VFB,
VDB, VSB, NPB, instruction cache bus, data cache bus) may be switched (this will not occur if
the same bus is accessed).
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User’s Manual U14559EJ3V1UM