V850E1 Datasheet, PDF (209/226 Pages) NEC – 32-Bit Microprocessor Core

APPENDIX B INSTRUCTION LIST
Table B-2. Instruction List (in Format Order) (1/3)
Format
Opcode
Mnemonic
Operand
15
0 31
16
I
0000000000000000
–
NOP
–
rrrrr000000RRRRR
–
MOV
reg1, reg2
rrrrr000001RRRRR
–
NOT
reg1, reg2
rrrrr000010RRRRR
–
DIVH
reg1, reg2
00000000010RRRRR
–
SWITCH
reg1
00000000011RRRRR
–
JMP
[reg1]
rrrrr000100RRRRR
–
SATSUBR
reg1, reg2
rrrrr000101RRRRR
–
SATSUB
reg1, reg2
rrrrr000110RRRRR
–
SATADD
reg1, reg2
rrrrr000111RRRRR
–
MULH
reg1, reg2
00000000100RRRRR
–
ZXB
reg1
00000000101RRRRR
–
SXB
reg1
00000000110RRRRR
–
ZXH
reg1
00000000111RRRRR
–
SXH
reg1
rrrrr001000RRRRR
–
OR
reg1, reg2
rrrrr001001RRRRR
–
XOR
reg1, reg2
rrrrr001010RRRRR
–
AND
reg1, reg2
rrrrr001011RRRRR
–
TST
reg1, reg2
rrrrr001100RRRRR
–
SUBR
reg1, reg2
rrrrr001101RRRRR
–
SUB
reg1, reg2
rrrrr001110RRRRR
–
ADD
reg1, reg2
rrrrr001111RRRRR
–
CMP
reg1, reg2
1111100001000000
–
DBTRAP^Note
–
II
rrrrr010000iiiii
–
MOV
imm5, reg2
rrrrr010001iiiii
–
SATADD
imm5, reg2
rrrrr010010iiiii
–
ADD
imm5, reg2
rrrrr010011iiiii
–
CMP
imm5, reg2
0000001000iiiiii
–
CALLT
imm6
rrrrr010100iiiii
–
SHR
imm5, reg2
rrrrr010101iiiii
–
SAR
imm5, reg2
rrrrr010110iiiii
–
SHL
imm5, reg2
rrrrr010111iiiii
–
MULH
imm5, reg2
III
ddddd1011dddCCCC
–
Bcond
disp9
Note Not supported in type C products
User’s Manual U14559EJ3V1UM
209