V850E1 Datasheet, PDF (28/226 Pages) NEC – 32-Bit Microprocessor Core

CHAPTER 2 REGISTER SET
Figure 2-10. Debug Interface Register (DIR) (3/3)
Notes 1. The IN, T1, T0, MT, and AT bits are not automatically cleared to 0 after being set to 1 (they are
cleared to 0 only by the LDSR instruction).
2. While the IN bit is set to 1, the T1 and T0 bits do not operate (even if a break occurs, these bits
are not set to 1), and are automatically cleared to 0.
3. The DM and CM bits change as follows.
Main
routine
Debug
monitor
routine 1
COMBO
interrupt
routine
Debug
monitor
routine 2
Debug
trap,
debug
break
Maskable/
non-maskable
interrupt
Debug
trap,
debug
break
DM CM
bit bit
0
0
1
0
User
mode
Debug
mode
User
mode
1
1
Debug
mode
User
0
mode
1
0
0
Debug
mode
User
mode
Notes 4. The T1, T0, MT, and AT bits cannot be arbitrarily set to 1 by a user program.
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User’s Manual U14559EJ3V1UM