V850E1 Datasheet, PDF (61/226 Pages) NEC – 32-Bit Microprocessor Core

CHAPTER 5 INSTRUCTIONS
<Special instruction>
CALLT
Call with table look up
Call with Table Look Up
Instruction format CALLT imm6
Operation
CTPC ← PC + 2 (return PC)
CTPSW ← PSW
adr ← CTBP + zero-extend (imm6 logically shift left by 1)
PC ← CTBP + zero-extend (Load-memory (adr, Halfword))
Format
Opcode
Format II
15
0
0000001000iiiiii
Flag
CY –
OV –
S
–
Z
–
SAT –
Explanation
Performs processing as follows.
<1> Transfers the restored PC and PSW contents to CTPC and CTPSW.
<2> Adds the CTBP value and the 6-bit immediate data logically shifted left by 1 bit and zero-
extended to word length, to generate a 32-bit table entry address.
<3> Loads the halfword of the address generated in step <2> and zero-extends to word
length.
<4> Adds the data of step <3> and the CTBP value to generate a 32-bit target address.
<5> Branches to the target address generated in step <4>.
Caution
If an interrupt is generated during instruction execution, the execution of that instruction may
stop after the end of the read/write cycle. Execution is resumed after returning from the
interrupt.
User’s Manual U14559EJ3V1UM
61