V850E1 Datasheet, PDF (190/226 Pages) NEC – 32-Bit Microprocessor Core

CHAPTER 9 SHIFTING TO DEBUG MODE
(a) Break due to setting breakpoints (2 channels)
The V850E1 CPU shifts to the debug mode based on the breakpoint settings (2 channels) validated when
the following break conditions are satisfied. The BPCn register is used to set each condition (n = 0, 1).
Caution While the IE bit of the BPCn register is set to 1, the system does not shift to the debug
mode if the BP ASID bit value and the program ID set to the ASID register do not match;
even if the break conditions match.
Table 9-1. Break Conditions
Type
Break Condition
Address^{Note 1}
Data
Execution
trap
Arbitrary
execution
address
Specific instruction
code
Specific instruction
code range
Specific
execution
address
Arbitrary instruction
code
Specific instruction
code
Specific instruction
code range
Specific
execution
address range
Arbitrary instruction
code
Specific instruction
code
Specific instruction
code range
Access
trap
Arbitrary
access
address
Specific data
Specific data range
Specific
access
address
Arbitrary data
Specific data
Specific data range
Specific
access
address range
Arbitrary data
Specific data
Specific data range
Break
Timing
BPxxn Register Setting^{Note 2} Setting of MD, FE, RE,
WE Bits of BPCn Register
BP BP BP BP MD
AVn AMn DVn DMn
Immediately <1> <1> √ <0> 0
before
execution
<1> <1> √
√
FE
1
RE,
WE
0^{Note 5}
√ <0> <1> <1> Any
√ <0> √ <0> 0
√ <0> √
√
√
√ <1> <1> Any
√
√
√ <0> 0
√
√
√
√
After
<1> <1> √ <0> 0
0
execution^{Note 3}
Immediately <1> <1> √
v
after
execution
After
√
execution^{Note 3}
√
<0> <1> <1> Any^{Note 4}
<0> √ <0> 0
√ <0> √
√
Immediately √
after
execution
√
<1> <1> Any^{Note 4}
After
√
√
√ <0> 0
execution^{Note 3}
√
√
√
√
0/1^{Note 6}
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User’s Manual U14559EJ3V1UM