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MC68HC08JK1 Datasheet, PDF (99/198 Pages) Motorola, Inc – HCMOS Microcontroller Unit
Freescale Semiconductor, Inc.
Monitor ROM (MON)
Functional Description
equal to the 2OSCOUT frequency, and OSC1 input directly generates
internal bus clocks. In this case, the OSC1 signal must have a 50% duty
cycle at maximum bus frequency.
In monitor mode, the COP is disabled as long as VDD + VHI is applied to
either the IRQ1 or the RST pin. (See Section 7. System Integration
Module (SIM) for more information on modes of operation.)
Enter monitor mode with the pin configuration shown above by pulling
RST low and then high. The rising edge of RST latches monitor mode.
Once monitor mode is latched, the values on the specified pins can
change.
Once out of reset, the MCU sends a break signal (10 consecutive logic
zeros) to the host computer, indicating that it is ready to receive a
command. The break signal also provides a timing reference to allow the
host to determine the necessary baud rate.
In monitor mode, the MCU uses different vectors for reset, SWI, and
break interrupt. The alternate vectors are in the $FE page instead of the
$FF page and allow code execution from the internal monitor firmware
instead of user code.
Table 9-2 is a summary of the vector differences between user mode
and monitor mode.
Table 9-2. Monitor Mode Vector Differences
Functions
Modes
COP
Reset Reset Break Break SWI
SWI
Vector Vector Vector Vector Vector Vector
High Low High Low High Low
User
Enabled $FFFE $FFFF $FFFC $FFFD $FFFC $FFFD
Monitor Disabled(1) $FEFE $FEFF $FEFC $FEFD $FEFC $FEFD
Notes:
1. If the high voltage (VDD + VHI) is removed from the IRQ1 pin or the RST pin, the SIM
asserts its COP enable output. The COP is a mask option enabled or disabled by the
COPD bit in the configuration register.
When the host computer has completed downloading code into the MCU
RAM, the host then sends a RUN command, which executes an RTI,
which sends control to the address on the stack pointer.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Monitor ROM (MON)
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Technical Data
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