MC68HC08JK1 Datasheet, PDF (151/198 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
External Interrupt (IRQ)
Functional Description
NOTE:
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.(See 7.6
Exception Control.)
ACK1
RESET
IRQPUD
VECTOR
FETCH
DECODER
V_DD
INTERNAL
PULLUP
DEVICE
IRQ1
V_DD
D ^CLR Q
CK
IRQ1
FF
SYNCHRO-
NIZER
IMASK1
IRQF1
TO CPU FOR
BIL/BIH
INSTRUCTIONS
IRQ1
INTERRUPT
REQUEST
MODE1
HIGH
VOLTAGE
DETECT
Figure 13-1. IRQ Module Block Diagram
TO MODE
SELECT
LOGIC
Addr.
$001D
Register Name
Bit 7
IRQ Status and Control ^{Read: 0}
Register Write:
(INTSCR) _{Reset: 0}
6
5
0
0
0
0
= Unimplemented
4
3
0
IRQF1
0
0
Figure 13-2. IRQ I/O Register Summary
2
0
ACK1
0
1
Bit 0
IMASK1 MODE1
0
0
13.4.1 IRQ1 Pin
A logic zero on the IRQ1 pin can latch an interrupt request into the IRQ1
latch. A vector fetch, software clear, or reset clears the IRQ1 latch.
If the MODE1 bit is set, the IRQ1 pin is both falling-edge-sensitive and
low-level-sensitive. With MODE1 set, both of the following actions must
occur to clear IRQ1:
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
External Interrupt (IRQ)
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Technical Data
151