MC68HC08JK1 Datasheet, PDF (86/198 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
System Integration Module (SIM)
SBSW — SIM Break Stop/Wait
This status bit is useful in applications requiring a return to wait or stop
mode after exiting from a break interrupt. Clear SBSW by writing a
logic zero to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it. The
following code is an example of this. Writing zero to the SBSW bit clears
it.
; This code works if the H register has been pushed onto the stack in the break
; service routine software. This code should be executed at the end of the
; break service routine software.
HIBYTE EQU 5
LOBYTE EQU 6
;
If not SBSW, do RTI
BRCLR SBSW,BSR, RETURN ; See if wait mode or stop mode was exited
; by break.
TST LOBYTE,SP
; If RETURNLO is not zero,
BNE DOLO
; then just decrement low byte.
DEC HIBYTE,SP
; Else deal with high byte, too.
DOLO DEC LOBYTE,SP
; Point to WAIT/STOP opcode.
RETURN PULH
RTI
; Restore H register.
7.8.2 Reset Status Register (RSR)
This register contains six flags that show the source of the last reset.
Clear the SIM reset status register by reading it. A power-on reset sets
the POR bit and clears all other bits in the register.
Technical Data
86
System Integration Module (SIM)
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MC68H(R)C08JL3 — Rev. 4
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