MC68HC08JK1 Datasheet, PDF (79/198 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
System Integration Module (SIM)
Exception Control
7.6.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an
interrupt regardless of the state of the interrupt mask (I bit) in the
condition code register.
NOTE: A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
7.6.2 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt
sources. Table 7-3 summarizes the interrupt sources and the interrupt
status register flags that they set. The interrupt status registers can be
useful for debugging.
Table 7-3. Interrupt Sources
Priority
Highest
Lowest
Source
Flag
Mask¹
INT
Register
Flag
Vector Address
Reset
—
—
—
$FFFE–$FFFF
SWI Instruction
—
—
—
$FFFC–$FFFD
IRQ1 Pin
IRQF1 IMASK1
IF1
$FFFA–$FFFB
Timer Channel 0 Interrupt
CH0F
CH0IE
IF3
$FFF6–$FFF7
Timer Channel 1 Interrupt
CH1F
CH1IE
IF4
$FFF4–$FFF5
Timer Overflow Interrupt
TOF
TOIE
IF5
$FFF2–$FFF3
Keyboard Interrupt
KEYF IMASKK
IF14
$FFE0–$FFE1
ADC Conversion Complete Interrupt
COCO
AIEN
IF15
$FFDE–$FFDF
Note:
1. The I bit in the condition code register is a global mask for all interrupts sources except the SWI
instruction.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
System Integration Module (SIM)
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Technical Data
79