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MC68HC08JK1 Datasheet, PDF (188/198 Pages) Motorola, Inc – HCMOS Microcontroller Unit
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Freescale Semiconductor, Inc.
Electrical Specifications
Table 18-7. DC Electrical Characteristics (3V)
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
NOTES:
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less
than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOP = 4MHz); all inputs 0.2 V from rail; no dc loads;
less than 100 pF on all outputs. CL = 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly af-
fects wait IDD.
5. STOP IDD measured with OSC1 grounded, no port pins sourcing current. LVI is disabled.
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until
minimum VDD is reached.
8. RPU1 and RPU2 are measured at VDD = 5.0V
18.10 3V Control Timing
Table 18-8. Control Timing (3V)
Characteristic(1)
Internal operating frequency(2)
RST input pulse width low(3)
Symbol
Min
fOP
—
tIRL
1.5
Max
Unit
4
MHz
—
µs
NOTES:
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VDD, unless otherwise
noted.
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this in-
formation.
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
Technical Data
188
Electrical Specifications
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MC68H(R)C08JL3 — Rev. 4
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