MC68HC08JK1 Datasheet, PDF (171/198 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Low Voltage Inhibit (LVI)
Low-Power Modes
Address: $001F
Bit 7
6
5
4
3
2
1
Read:
COPRS R
Write:
R
LVID
R
SSREC STOP
Reset: 0
0
0
0
0
0
0
R = Reserved
Figure 16-3. Configuration Register 1 (CONFIG1)
Bit 0
COPD
0
LVID — Low Voltage Inhibit Disable Bit
1 = Low voltage inhibit disabled
0 = Low voltage inhibit enabled
LVIT1, LVIT0 — LVI Trip Voltage Selection
These two bits determine at which level of V_DD the LVI module will
come into action. LVIT1 and LVIT0 are cleared by a Power-On Reset
only.
LVIT1
0
0
1
1
LVIT0
0
1
0
1
Trip Voltage⁽¹⁾
V_LVR3 (2.4V)
V_LVR3 (2.4V)
V_LVR5 (4.0V)
Reserved
Comments
For V_DD=3V operation
For V_DD=3V operation
For V_DD=5V operation
1. See Section 18. Electrical Specifications for full parameters.
16.6 Low-Power Modes
The STOP and WAIT instructions put the MCU in low-power-
consumption standby modes.
16.6.1 Wait Mode
The LVI module, when enabled, will continue to operate in WAIT Mode.
16.6.2 Stop Mode
The LVI module, when enabled, will continue to operate in STOP Mode.
MC68H(R)C08JL3 — Rev. 4
MOTOROLA
Low Voltage Inhibit (LVI)
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Technical Data
171