MC68HC08JK1 Datasheet, PDF (98/198 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Monitor ROM (MON)
9.4.1 Entering Monitor Mode
Table 9-1 shows the pin conditions for entering monitor mode. As
specified in the table, monitor mode may be entered after a POR and will
allow communication at 9600 baud provided one of the following sets of
conditions is met:
1. If IRQ1 = V_DD + V_HI:
– OSC1 is 4.9125MHz
– PTB3 = low
2. If IRQ1 = V_DD + V_HI:
– OSC1 is 9.8304MHz
– PTB3 = high
Table 9-1. Monitor Mode Entry Requirements and Options
Clock Source
and
Frequency
Bus
Frequency
Comments
V_DD + V_HI 0 0 1 1
V_DD + V_HI 1 0 1 1
OSC1 at
4.9152 MHz
OSC1 at
9.8304 MHz
2.4576 MHz
2.4576 MHz
Bypasses RC oscillator (in
HRC08xxx); OSC1 input
must be x-tal oscillator or
external oscillator clock.
9600 baud communication
on PTB0. COP disabled.
X-tal or RC
XTALCLK ÷ 4
V_DD
XXXX
oscillator at
or
Enters User mode
desired frequency RCCLK ÷ 4
Notes:
1. PTB3 = 0: Bypasses the divide-by-two prescaler to SIM.
The OSC1 clock must be 50% duty cycle for this condition.
2. XTALCLK is the X-tal oscillator output, for MC68HC08xxx. See Figure 8-1.
4. RCCLK is the RC oscillator output, for MC68HRC08xxx. See Figure 8-2.
5. See Table 18-4 for V_DD + V_HI voltage level requirements.
If V_DD +V_HI is applied to IRQ1 and PTB3 is low upon monitor mode entry
(Table 9-1 condition set 1), the bus frequency is a divide-by-two of the
clock input to OSC1. If PTB3 is high with V_DD +V_HI applied to IRQ1 upon
monitor mode entry (Table 9-1 condition set 2), the bus frequency is a
divide-by-four of the clock input to OSC1. Holding the PTB3 pin low
when entering monitor mode causes a bypass of a divide-by-two stage
at the internal clock circuit. In this event, the OSCOUT frequency is
Technical Data
98
Monitor ROM (MON)
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MC68H(R)C08JL3 — Rev. 4
MOTOROLA