MC68HC08JK1 Datasheet, PDF (140/198 Pages) Motorola, Inc – HCMOS Microcontroller Unit

I/O Ports
Freescale Semiconductor, Inc.
12.3.2 Data Direction Register A (DDRA)
Data direction register A determines whether each port A pin is an input
or an output. Writing a logic one to a DDRA bit enables the output buffer
for the corresponding port A pin; a logic zero disables the output buffer.
Address: $0004
Bit 7
6
5
4
3
2
1
Read: 0
Write:
DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1
Reset: 0
0
0
0
0
0
0
Figure 12-3. Data Direction Register A (DDRA)
Bit 0
DDRA0
0
DDRA[6:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[6:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE: Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 12-4 shows the port A I/O logic.
Technical Data
140
I/O Ports
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MC68H(R)C08JL3 — Rev. 4
MOTOROLA