MC68HC08JK1 Datasheet, PDF (164/198 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Computer Operating Properly (COP)
15.3 Functional Description
Figure 15-1 shows the structure of the COP module.
2OSCOUT
SIM
12-BIT SIM COUNTER
SIM RESET CIRCUIT
RESET STATUS REGISTER
INTERNAL RESET SOURCES⁽¹⁾
RESET VECTOR FETCH
COPCTL WRITE
COPEN (FROM SIM)
COPD (FROM CONFIG1)
RESET
COPCTL WRITE
COP CLOCK
COP MODULE
6-BIT COP COUNTER
CLEAR
COP COUNTER
NOTE:
COP RATE SEL
(COPRS FROM CONFIG1)
1. See SIM section for more details.
Figure 15-1. COP Block Diagram
The COP counter is a free-running 6-bit counter preceded by the 12-bit
system integration module (SIM) counter. If not cleared by software, the
COP counter overflows and generates an asynchronous reset after
2¹⁸ – 2⁴ or 2¹³ – 2⁴ 2OSCOUT cycles; depending on the state of the
COP rate select bit, COPRS, in configuration register 1. With a 2¹⁸ – 2⁴
2OSCOUT cycle overflow option, a 8MHz crystal gives a COP timeout
period of 32.766 ms. Writing any value to location $FFFF before an
overflow occurs prevents a COP reset by clearing the COP counter and
stages 12 through 5 of the SIM counter.
Technical Data
164
Computer Operating Properly (COP)
For More Information On This Product,
Go to: www.freescale.com
MC68H(R)C08JL3 — Rev. 4
MOTOROLA