MC9S08GB60 Datasheet, PDF (89/290 Pages) Motorola, Inc – Microcontrollers

Parallel I/O Registers and Control Bits
PTCDDn — Data Direction for Port C Bit n (n = 0–7)
These read/write bits control the direction of port C pins and what is read for PTCD reads.
1 = Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn.
0 = Input (output driver disabled) and reads return the pin value.
6.6.4 Port D Registers (PTDD, PTDPE, PTDSE, and PTDDD)
Port D includes eight pins shared between general-purpose I/O, TPM1, and TPM2. Port D pins used as
general-purpose I/O pins are controlled by the port D data (PTDD), data direction (PTDDD), pullup enable
(PTDPE), and slew rate control (PTDSE) registers.
If a TPM takes control of a port D pin, the corresponding PTDDD bit is ignored. When the TPM is in
output compare mode, the corresponding PTDSE can be used to provide slew rate on the pin. When the
TPM is in input capture mode, the corresponding PTDPE can be used, provided the corresponding
PTDDD bit is 0, to provide a pullup device on the pin.
Reads of PTDD will return the logic value of the corresponding pin, provided PTDDD is 0.
PTDD
PTDPE
PTDSE
PTDDD
Bit 7
Read:
PTDD7
Write:
Reset: 0
6
PTDD6
0
5
PTDD5
0
4
PTDD4
0
3
PTDD3
0
2
PTDD2
0
1
PTDD1
0
Bit 0
PTDD0
0
Read:
PTDPE7 PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0
Write:
Reset: 0
0
0
0
0
0
0
0
Read:
PTDSE7 PTDSE6 PTDSE5 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0
Write:
Reset: 0
0
0
0
0
0
0
0
Read:
PTDDD7 PTDDD6 PTDDD5 PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 6-12. Port D Registers
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
89