MC9S08GB60 Datasheet, PDF (257/290 Pages) Motorola, Inc – Microcontrollers

Registers and Control Bits
ARMF — Arm Flag
While DBGEN = 1, this status bit is a read-only image of the ARM bit in DBGC. This bit is set by
writing 1 to the ARM control bit in DBGC (while DBGEN = 1) and is automatically cleared at the end
of a debug run. A debug run is completed when the FIFO is full (begin trace) or when a trigger event
is detected (end trace). A debug run can also be ended manually by writing 0 to the ARM or DBGEN
bits in DBGC.
1 = Debugger armed.
0 = Debugger not armed.
CNT3:CNT2:CNT1:CNT0 — FIFO Valid Count
These bits are cleared at the start of a debug run and indicate the number of words of valid data in the
FIFO at the end of a debug run. The value in CNT does not decrement as data is read out of the FIFO.
The external debug host is responsible for keeping track of the count as information is read out of the
FIFO.
Table 15-3. CNT Status Bits
CNT[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
Valid Words in FIFO
No valid data
1
2
3
4
5
6
7
8
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
257