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MC9S08GB60 Datasheet, PDF (58/290 Pages) Motorola, Inc – Microcontrollers | |||
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Chapter 4 Memory
4.6.5 FLASH Status Register (FSTAT)
Bits 3, 1, and 0 always read 0 and writes have no meaning or effect. The remaining ï¬ve bits are status bits
that can be read at any time. Writes to these bits have special meanings that are discussed in the bit
descriptions.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
FCCF
0 FBLANK 0
0
FCBEF
FPVIOL FACCERR
Write:
Reset: 1
1
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-8. FLASH Status Register (FSTAT)
FCBEF â FLASH Command Buffer Empty Flag
The FCBEF bit is used to launch commands. It also indicates that the command buffer is empty so that
a new command sequence can be executed when performing burst programming. The FCBEF bit is
cleared by writing a 1 to it or when a burst program command is transferred to the array for
programming. Only burst program commands can be buffered.
1 = A new burst program command may be written to the command buffer.
0 = Command buffer is full (not ready for additional commands).
FCCF â FLASH Command Complete Flag
FCCF is set automatically when the command buffer is empty and no command is being processed.
FCCF is cleared automatically when a new command is started (by writing 1 to FCBEF to register a
command). Writing to FCCF has no meaning or effect.
1 = All commands complete
0 = Command in progress
FPVIOL â Protection Violation Flag
FPVIOL is set automatically when FCBEF is cleared to register a command that attempts to erase or
program a location in a protected block (the erroneous command is ignored). FPVIOL is cleared by
writing a 1 to FPVIOL.
1 = An attempt was made to erase or program a protected location.
0 = No protection violation.
FACCERR â Access Error Flag
FACCERR is set automatically when the proper command sequence is not followed exactly (the
erroneous command is ignored), if a program or erase operation is attempted before the FCDIV register
has been initialized, or if the MCU enters stop while a command was in progress. For a more detailed
discussion of the exact actions that are considered access errors, see Section 4.4.5, âAccess Errors.â
FACCERR is cleared by writing a 1 to FACCERR. Writing a 0 to FACCERR has no meaning or effect.
1 = An access error has occurred.
0 = No access error has occurred.
MC9S08GB/GT Data Sheet, Rev. 2.3
58
Freescale Semiconductor
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