MC9S08GB60 Datasheet, PDF (216/290 Pages) Motorola, Inc – Microcontrollers

Inter-Integrated Circuit (IIC) Module
RSTA — Repeat START
Writing a one to this bit will generate a repeated START condition provided it is the current master.
This bit will always be read as a low. Attempting a repeat at the wrong time will result in loss of
arbitration.
13.5.4 IIC Status Register (IIC1S)
Bit 7
6
5
4
3
2
1
Bit 0
Read: TCF
BUSY
0
SRW
RXAK
IAAS
ARBL
IICIF
Write:
Reset: 1
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-8. IIC Status Register (IIC1S)
TCF — Transfer Complete Flag
This bit is set on the completion of a byte transfer. Note that this bit is only valid during or immediately
following a transfer to the IIC module or from the IIC module.The TCF bit is cleared by reading the
IIC1D register in receive mode or writing to the IIC1D in transmit mode.
1 = Transfer complete.
0 = Transfer in progress.
IAAS — Addressed as a Slave
The IAAS bit is set when its own specific address is matched with the calling address. Writing the
IIC1C register clears this bit.
1 = Addressed as a slave.
0 = Not addressed.
BUSY — Bus Busy
The BUSY bit indicates the status of the bus regardless of slave or master mode. The BUSY bit is set
when a START signal is detected and cleared when a STOP signal is detected.
1 = Bus is busy.
0 = Bus is idle.
ARBL — Arbitration Lost
This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be cleared by
software, by writing a one to it.
1 = Loss of arbitration.
0 = Standard bus operation.
MC9S08GB/GT Data Sheet, Rev. 2.3
216
Freescale Semiconductor