MC9S08GB60 Datasheet, PDF (173/290 Pages) Motorola, Inc – Microcontrollers

INTERNAL BUS
16 × BAUD
RATE CLOCK
DIVIDE
BY 16
FROM RxD1 PIN
M
DATA RECOVERY
LOOPS
RSRC
SINGLE-WIRE
LOOP CONTROL
FROM
TRANSMITTER
WAKE
ILT
(READ-ONLY)
SCID – Rx BUFFER
Receiver Functional Description
11-BIT RECEIVE SHIFT REGISTER
H876543210L
SHIFT DIRECTION
WAKEUP
LOGIC
RWU
RDRF
RIE
IDLE
ILIE
Rx INTERRUPT
REQUEST
OR
ORIE
FE
FEIE
ERROR INTERRUPT
REQUEST
NF
NEIE
PE
PARITY
PT
CHECKING
PF
PEIE
Figure 11-4. SCI Receiver Block Diagram
The receiver is enabled by setting the RE bit in SCIxC2. Character frames consist of a start bit of logic 0,
eight (or nine) data bits (LSB first), and a stop bit of logic 1. For information about 9-bit data mode, refer
to Section 11.8.1, “8- and 9-Bit Data Modes.” For the remainder of this discussion, we assume the SCI is
configured for normal 8-bit data mode.
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
173