MC9S08GB60 Datasheet, PDF (224/290 Pages) Motorola, Inc – Microcontrollers

Analog-to-Digital Converter (ATD) Module
conversion to the mode control unit. For V_REFL and V_REFH, the SAR machine uses the reference potentials
to set the sampled signal level within itself without relying on the S/H machine to deliver them.
The mode control unit organizes the conversion, specifies the input sample channel, and moves the digital
output data from the SAR register to the result register. The result register consists of a dual-port register.
The SAR register writes data into the register through one port while the module data bus reads data out
of the register through the other port.
14.3.2 Sample and Hold
The S/H machine accepts analog signals and stores them as capacitor charge on a storage node located in
the SAR machine. Only one sample can be held at a time so the S/H machine and the SAR machine can
not run concurrently even though they are independent machines. Figure 14-3 shows the placement of the
various resistors and capacitors.
V_AIN
+
–
R_AS
C_AS
INPUT PIN _RAIN1
INPUT PIN
CHANNEL
SELECT 0
R_AIN2
INPUT PIN
CHANNEL
SELECT 1
R_AIN3
INPUT PIN
. CHANNEL
. SELECT 2
.
R_AINn
CHANNEL
SELECT n
C_AIN
ATD SAR
ENGINE
Figure 14-3. Resistor and Capacitor Placement
When the S/H machine is not sampling, it disables its own internal clocks.The input analog signals are
unipolar. The signals must fall within the potential range of V_SSAD to V_DDAD. The S/H machine is not
required to perform special conversions (i.e., convert V_REFL and V_REFH).
Proper sampling is dependent on the following factors:
• Analog source impedance (the real portion, R_AS – see Appendix A, “Electrical Characteristics”)
— This is the resistive (or real, in the case of high frequencies) portion of the network driving the
analog input voltage V_AIN.
• Analog source capacitance (C_AS) — This is the filtering capacitance on the analog input, which (if
large enough) may help the analog source network charge the ATD input in the case of high R_AS.
• ATD input resistance (R_AIN – maximum value 7 kΩ) — This is the internal resistance of the ATD
circuit in the path between the external ATD input and the ATD sample and hold circuit. This
resistance varies with temperature, voltage, and process variation but a worst case number is
necessary to compute worst case sample error.
MC9S08GB/GT Data Sheet, Rev. 2.3
224
Freescale Semiconductor