MC9S08GB60 Datasheet, PDF (86/290 Pages) Motorola, Inc – Microcontrollers

Chapter 6 Parallel Input/Output
PTASEn — Slew Rate Control Enable for Port A Bit n (n = 0–7)
For port A pins that are outputs, these read/write control bits determine whether the slew rate
controlled outputs are enabled. For port A pins that are configured as inputs, these bits are ignored.
1 = Slew rate control enabled.
0 = Slew rate control disabled.
PTADDn — Data Direction for Port A Bit n (n = 0–7)
These read/write bits control the direction of port A pins and what is read for PTAD reads.
1 = Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
0 = Input (output driver disabled) and reads return the pin value.
6.6.2 Port B Registers (PTBD, PTBPE, PTBSE, and PTBDD)
Port B includes eight general-purpose I/O pins that share with the ATD function. Port B pins used as
general-purpose I/O pins are controlled by the port B data (PTBD), data direction (PTBDD), pullup enable
(PTBPE), and slew rate control (PTBSE) registers.
If the ATD takes control of a port B pin, the corresponding PTBDD, PTBSE, and PTBPE bits are ignored.
When a port B pin is being used as an ATD pin, reads of PTBD will return a 0 of the corresponding pin,
provided PTBDD is 0.
PTBD
PTBPE
PTBSE
PTBDD
Bit 7
Read:
PTBD7
Write:
Reset: 0
6
PTBD6
0
5
PTBD5
0
4
PTBD4
0
3
PTBD3
0
2
PTBD2
0
1
PTBD1
0
Bit 0
PTBD0
0
Read:
PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0
Write:
Reset: 0
0
0
0
0
0
0
0
Read:
PTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0
Write:
Reset: 0
0
0
0
0
0
0
0
Read:
PTBDD7 PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDD0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 6-10. Port B Registers
MC9S08GB/GT Data Sheet, Rev. 2.3
86
Freescale Semiconductor