MC9S08GB60 Datasheet, PDF (198/290 Pages) Motorola, Inc – Microcontrollers

Serial Peripheral Interface (SPI) Module
SSOE — Slave Select Output Enable
This bit is used in combination with the mode fault enable (MODFEN) bit in SPCR2 and the
master/slave (MSTR) control bit to determine the function of the SS1 pin as shown in Table 12-1.
Table 12-1. SS1 Pin Function
MODFEN
0
0
1
1
SSOE
0
1
0
1
Master Mode
General-purpose I/O (not SPI)
General-purpose I/O (not SPI)
SS input for mode fault
Automatic SS output
Slave Mode
Slave select input
Slave select input
Slave select input
Slave select input
LSBFE — LSB First (Shifter Direction)
1 = SPI serial data transfers start with least significant bit.
0 = SPI serial data transfers start with most significant bit.
12.4.2 SPI Control Register 2 (SPI1C2)
This read/write register is used to control optional features of the SPI system. Bits 7, 6, 5, and 2 are not
implemented and always read 0.
Read:
Write:
Reset:
Bit 7
6
0
0
5
4
3
2
0
0
MODFEN BIDIROE
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-8. SPI Control Register 2 (SPI1C2)
1
Bit 0
SPISWAI SPC0
0
0
MODFEN — Master Mode-Fault Function Enable
When the SPI is configured for slave mode, this bit has no meaning or effect. (The SS1 pin is the slave
select input.) In master mode, this bit determines how the SS1 pin is used (refer to Table 12-1 for more
details).
1 = Mode fault function enabled, master SS1 pin acts as the mode fault input or the slave select
output.
0 = Mode fault function disabled, master SS1 pin reverts to general-purpose I/O not controlled by
SPI.
MC9S08GB/GT Data Sheet, Rev. 2.3
198
Freescale Semiconductor