MC9S08GB60 Datasheet, PDF (212/290 Pages) Motorola, Inc – Microcontrollers

Inter-Integrated Circuit (IIC) Module
13.5 IIC Registers and Control Bits
This section consists of the IIC register descriptions in address order.
Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address
assignments for all IIC registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
13.5.1 IIC Address Register (IIC1A)
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
ADDR
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-5. IIC Address Register (IIC1A)
1
Bit 0
0
0
0
ADDR — IIC Address Register
The ADDR contains the specific slave address to be used by the IIC module. This is the address the
module will respond to when addressed as a slave.
13.5.2 IIC Frequency Divider Register (IIC1F)
Bit 7
6
5
4
3
2
1
Bit 0
Read:
MULT
ICR
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 13-6. IIC Frequency Divider Register (IIC1F)
MULT — IIC Multiplier Factor
The MULT bits define the multiplier factor mul. This factor is used along with the SCL divider to
generate the IIC baud rate. Table 13-2 provides the multiplier factor mul as defined by the MULT bits.
Table 13-2. Multiplier Factor
MULT
00
01
10
11
mul
01
02
04
Reserved
MC9S08GB/GT Data Sheet, Rev. 2.3
212
Freescale Semiconductor