MC9S08GB60 Datasheet, PDF (105/290 Pages) Motorola, Inc – Microcontrollers

Functional Description
CLKST
CLKS
RFD
REFERENCE
DIVIDER (/7)
RANGE
MFD
ICGIRCLK
FLT
CLOCK
SELECT
CIRCUIT
ICGDCLK
REDUCED
FREQUENCY
ICGOUT
DIVIDER (R)
SUBTRACTOR
DIGITAL
LOOP
FILTER
CLKST
DIGITALLY ^1x
CONTROLLED
OSCILLATOR
2x
FLL ANALOG
OVERFLOW
COUNTER ENABLE
RANGE
LOCK AND
LOSS OF CLOCK
DETECTOR
PULSE
COUNTER
ICG2DCLK
RESET AND
INTERRUPT
CONTROL
FREQUENCY-
LOCKED
LOOP (FLL)
IRQ
RESET
DCOS LOCK LOLS LOCS ERCS
ICGIF LOLRE LOCRE
Figure 7-6. Detailed Frequency-Locked Loop Block Diagram
7.3.3 FLL Engaged, Internal Clock (FEI) Mode
FLL engaged internal (FEI) is entered when any of the following conditions occur:
• CLKS bits are written to 01
• The DCO clock stabilizes (DCOS = 1) while in SCM upon exiting the off state with CLKS = 01
In FLL engaged internal mode, the reference clock is derived from the internal reference clock
ICGIRCLK, and the FLL loop will attempt to lock the ICGDCLK frequency to the desired value, as
selected by the MFD bits.
7.3.3.1 FLL Engaged Internal Unlocked
FEI unlocked is a temporary state that is entered when FEI is entered and the count error (∆n) output from
the subtractor is greater than the maximum n_unlock or less than the minimum n_unlock, as required by the
lock detector to detect the unlock condition.
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
105