MC68HC05E0 Datasheet, PDF (72/96 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit

8.3
I2C-Bus Configuration
The I2C-bus protocol was specified by Philips. It consists of a bidirectional data line (SDA) and a
bidirectional clock line (SCL). Each driver connected to the SDA and SCL lines should be
open-drain. An off-chip pull-up resistor (4k7) pulls either line to a high state if the line is not being
held low by an active peripheral. SDA and SCL pulled high is the I2C idle state.
The original I2C-bus specification allows for different devices connected to an SDA and SCL line
to be receivers, transmitters, masters (generating the SCL clock) or slaves. In the MC68HC05E0
implementation, the micro is always master.
A variety of devices exist which can communicate over the I2C-bus, from complex microcontrollers
(e.g. Philips 68070) to real-time clock chips, LCD drivers and “dumb” serial EEPROMs. The
I2C-bus implementation on the MC68HC05E0 is intended for use in simpler bus systems, rather
than complex multi-master systems. For this reason the following features of the full I2C-bus
protocol are NOT supported:
– The passing of bus mastery from one peripheral to another. (The
MC68HC05E0 is always bus master).
– Clock synchronization when two bus masters simultaneously drive SCL.
8
– Detection of data collision (2 devices sending data simultaneously).
– Address register and comparator to allow selection of which peripheral is to
be addressed. (No I2C-bus address register is available on the
MC68HC05E0)
The I2C-bus specification calls for a pause of at least 4.7 µs between the end of one transmission
sequence and the start of another. This is not done in hardware by the MC68HC05E0 but, as at
least three instructions are needed to load/read, set-up and start the I2C-bus circuit, the pause
will always be greater than 5 µs when using a 4 MHz crystal. If an 8 MHz crystal is used, software
must provide a delay greater than 4.7 µs. The user has control over whether START and STOP
bits are generated. Also, the I2C-bus can be programmed such that the micro does or does not
provide an acknowledge signal to peripherals.
The I2C-bus circuitry monitors the bus continuously to check that no other I2C-bus peripheral is
currently using the bus.
Figure 8-3 shows the timing relationship between the clock (SCL) and data (SDA) in I2C-bus
mode. Refer to Section 9 for more detailed timing information.
MOTOROLA
8-6
SERIAL INTERFACE
MC68HC05E0