MC68HC05E0 Datasheet, PDF (66/96 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit

The RTI system is controlled via the RTI Control Register ($0018).
RTI control register
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0018
RTIF
RTIE
RT1 RT0 0000 0011
RTIF is a clearable, read-only status bit and is set when the output of the chosen selector stage
(1 of 4) goes active. A CPU interrupt request will be generated (IRQB) if the Real Time Interrupt
is enabled. Clearing the RTIF bit is done by writing a “zero” to it. Writing a “one” to RTIF has no
effect. Reset clears RTIF.
RTIF
1 (set) – RTI function has timed out and generated interrupt signal.
0 (clear) – RTI function has not timed out.
7
RTIE is a read/write control bit which allows the Real Time Interrupt to generate a CPU interrupt
request (IRQ). Reset clears RTIE.
RTIE
1 (set) – RTI request enabled
0 (clear) – RTI request disabled
RT1, RT0 select one of four taps from the Real Time Interrupt Select logic. On reset, these bits
are set to “one” which selects the lowest periodic interrupt rate, and gives the maximum time in
which to modify the bits to select a different time-out period. Care should be taken when altering
RT1 and RT0 if a timeout is imminent or uncertain; if a tap is selected during a cycle in which the
counter is switching, an interrupt request could be missed, or an additional one generated.
Table 7-2 Real Time Interrupt Rates (bus frequency = 4MHz)
RT1 RT0 RTI time-out period (ms)
0
0
4.1
0
1
8.2
1
0
16.4
1
1
32.8
MOTOROLA
7-6
TIMERS
MC68HC05E0