MC68HC05E0 Datasheet, PDF (15/96 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit

1
1
INTRODUCTION
1.1
General
The MC68HC05E0 is a high-performance fully-expandable ROM-less member of the M68HC05
Family of microcomputers. The M68HC05 CPU core has been enhanced with two powerful,
independently controlled timer subsystems, and a serial interface (SI) which can operate in either
SPI (Serial Peripheral Interface) or I2C-bus compatible mode. An external 16-bit address/8-bit
data expansion bus and chip-select logic are provided to allow access to external ROM, RAM and
I/O. The MC68HC05E0, with 480 bytes of on-chip RAM and 36 I/O port lines, is available in a
68-pin PLCC package.
1.2
Features
• Industry-standard M68HC05 core and instruction set
• 64 kbyte address range
• 16-bit address/8-bit data expansion bus to interface to external memory and peripherals
• Address decoder provides select logic for internal and external areas of the memory map
• 480 bytes of on-chip RAM.
• 4 MHz bus frequency
• Programmable system timing control
• 36 I/O lines (four 8-bit bidirectional ports, one 4-bit bidirectional port)
• LED drive capability on 8 I/O pins (Port A)
• 6-bit timer with 8-bit prescaler
• 14-bit timer with 8-bit scaler
• Programmable Real Time Interrupt
MC68HC05E0
INTRODUCTION
MOTOROLA
1-1