MC68HC05E0 Datasheet, PDF (62/96 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit

The maximum bus clock frequency (P02) is 4 MHz. One of four different sub-system clock
frequencies can be selected via bits 6 and 7 (SC0 and SC1) of the Timer Control Register ($000C)
(see Table 7-1).
Table 7-1 Sub-system Clock Frequency Selection
SC1
SC0
Sub-system clock frequency (f_SUB)
0
0
P02÷8
0
1
P02÷4
1
0
P02÷2
1
1
P02÷1
A Timer Stop signal on the active low TS pin allows Timer A and Timer B to be halted. TS can be
used as a gate input to the two timers, thereby allowing pulse width measurement to be carried
7
out on the input signal. Halting the timers is also useful during emulation of the device and during
software debug. The SPI/I2C functions are not interrupted by the TS signal.
7.2
Timer A
Timer A consists of an 8-bit prescaler driving a 6-bit free-running counter (see Figure 7-2).
CETA
Sub-system
Clock
Frequency
INTMA
OF
8 Bit
6 Bit
(freerunning)
Timer A
Prescaler Register
$000A
INTFA
Figure 7-2 Timer A Structure
INT2
(16 µs - 32 ms)
MOTOROLA
7-2
TIMERS
MC68HC05E0