MC68HC05E0 Datasheet, PDF (44/96 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit

4.2.3.4 Timer A Interrupt
The interrupt request is latched when Timer A times out. It is then synchronized internally and
serviced by the routine that has its address contained in memory locations $FFF8 and $FFF9. The
Timer A Interrupt Mask bit (INTMA) in the Interrupt Control Register ($000E) allows this interrupt
to be masked from the processor.
4 4.2.3.5 Timer B Interrupt
The interrupt request is latched when Timer B times out. It is then synchronized internally and
serviced by the routine that has its start address contained in memory locations $FFF6 and
$FFF7. The Timer B Interrupt Mask bit (INTMB) in the Interrupt Control Register ($000E) allows
this interrupt to be masked from the processor.
4.2.3.6 SI Interrupt
The interrupt request is latched immediately after each data transfer. It is then synchronized
internally and serviced by the routine that has its start address contained in memory locations
$FFF4 and $FFF5. The SI Enable bit (SIE) in the Port E/SI Mode Register ($0010) allows this
interrupt to be enabled or disabled (see Section 8).
4.2.4 Interrupt Control
The Interrupt Control Register ($000E) allows masking and provides acknowledgement of the
interrupt signals:
Interrupt control register
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$000E WAKF INTXP INTFB INTFA INTFX INTMB INTMA INTMX 0000 0001
INTMX, INTMA, INTMB
These three interrupt mask bits permit INTX (external interrupt), Timer A and Timer B interrupt
signals to be masked from the processor:
1 (set) – Interrupts not masked
0 (clear) – Interrupts masked
After a hardware reset, only external interrupts are permitted.
MOTOROLA
4-8
RESETS, INTERRUPTS AND LOW POWER MODES
MC68HC05E0