MC68HC05E0 Datasheet, PDF (64/96 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit

7.4
Control Registers for Timer A and Timer B
Timer A and Timer B are enabled/disabled via the CETA (Count Enable Timer A) and CETB (Count
Enable Timer B) control bits in the Timer Control Register ($000C).
Timer control register
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$000C SC1 SC0 PITX PITW 1 XROM CETB CETA 0000 1100
CETA, CETB
1 (set) – Counter enabled
0 (clear) – Counter disabled
Both timers generate a signal on overflow which can be used to interrupt the processor. These
signals can be masked by the INTMA and INTMB bits in the Interrupt Control Register ($000E).
7
Timer Interrupt Flag and Acknowledge bits INTFA and INTFB indicate when a timer interrupt has
occurred and can be written to reset the timer interrupt logic.
Interrupt control register
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$000C WAKF INTXP INTFB INTFA INTFX INTMB INTMA INTMX 0000 0001
INTMA, INTMB
1 (set) – Interrupts not masked
0 (clear) – Interrupts masked
INTFA, INTF
1 (set) – Interrupt has occurred
0 (clear) – Interrupt has not occurred
Writing a “0” to INTFA or INTFB acknowledges the interrupt and resets the interrupt signal for that
timer.
MOTOROLA
7-4
TIMERS
MC68HC05E0