MC68HC05E0 Datasheet, PDF (40/96 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit

Table 4-1 shows the relative priority of all the possible interrupt sources. Internally, the External
Interrupt, Real Time Interrupt, and Wake-up signals are “ORed” to generate the CPU interrupt
signal IRQB. The source responsible for generating the IRQB interrupt can be determined by
examining the interrupt flag bits associated with these sources.
Note: The external interrupt INTX can be disabled by setting the External Interrupt Mask bit
4
(INTMX) in the Interrupt Control Register ($000E).
Table 4-1 Interrupt Priorities
Source
Real time interrupt
External interrupt (INTX)
Wake-up (Port C)
Timer A
Timer B
Serial interface
Vector address
$FFFA, $FFFB
$FFF8, $FFF9
$FFF6, $FFF7
$FFF4, $FFF5
Priority
highest
lowest
For example, if both an external interrupt and a Timer A interrupt are pending at the end of an
instruction execution, the external interrupt is serviced first.
The software interrupt SWI is executed in the same way as any other instruction, regardless of the
state of the I-bit.
4.2.1 Hardware Controlled Interrupt Sequence
The following three functions (RESET, STOP, and WAIT) are not in the strictest sense interrupts.
However, they are acted upon in a similar manner. Flowcharts for hardware interrupts are shown
in Figure 4-3, and for STOP and WAIT in Figure 4-4.
RESET: A reset condition causes the program to vector to its starting address which is specified
by the contents of memory locations $FFFE (MSB) and $FFFF (LSB). The I bit in the
condition code register is also set.
STOP:
The STOP instruction causes the oscillator to be turned off and the processor to “sleep”
until an external interrupt (INTX) (if enabled), a wake-up interrupt (if enabled) or reset
occurs.
WAIT:
The WAIT instruction causes all processor clocks to stop, but leaves the timer clock
running. This “rest” state of the processor can be cleared by reset, an external interrupt
(INTX) (if enabled), a wake-up interrupt or a Timer/SI interrupt. There are no special
wait vectors for these individual interrupts.
MOTOROLA
4-4
RESETS, INTERRUPTS AND LOW POWER MODES
MC68HC05E0