MC68HC05E0 Datasheet, PDF (39/96 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit

When the current instruction is complete, the processor checks all pending hardware interrupts. If
interrupts are not masked (CCR I bit clear), the processor proceeds with interrupt processing;
otherwise, the next instruction is fetched and executed.
Internal circuitry generates a processor interrupt signal IRQB if an interrupt occurs via either the
external interrupt pin INTX, the wake-up function on Port C, or a real time interrupt (see
Figure 4-2). The interrupting source can be determined by testing the state of the INTFX, WAKF
and RTIF flag bits.
4
Wake-up (Port C)
Real Time Interrupt
RTIE
WAKF
IRQB
RTIF
INTFX
INTMX
INTXP
Pad
INTX
Figure 4-2 Internal Processor Interrupt Signal IRQB
Note:
Acknowledging an interrupt signal too early could have an effect on the BIH and BIL
command functions.
MC68HC05E0
RESETS, INTERRUPTS AND LOW POWER MODES
MOTOROLA
4-3