MC68HC05E0 Datasheet, PDF (59/96 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit

Port E
Data
Register
($0004)
SI Data Register ($000F)
SPI
Control
Logic
I ²C
Control
Logic
Selection
Logic
PS1 PS0
Figure 6-4 Port E Structure
E0
E1
Port E
6
Pads
E2
E3
6.5
Other Port Considerations
All ports are latched with the bus timing signal P02 (especially for inputs).
All output ports can emulate open-drain outputs. This is achieved by writing a zero to the relevant
output port latch. By toggling the corresponding data direction bit, the port pin will either be an
output zero or tri-state (an input). Refer to Figure 6-5.
When using a port pin as an open-drain output, certain precautions must be taken in the user
software. If a read-modify-write instruction is used on a port where the open-drain is assigned and
the pin at this time is programmed as an input, it will read it as a “one”. The read-modify-write
instruction will then write this “one” into the output data latch on the next cycle. This would cause
the open-drain pin not to output a “zero” when desired.
Note: “Open-drain” outputs should not be pulled above VDD.
MC68HC05E0
PARALLEL INPUT/OUTPUT PORTS
MOTOROLA
6-7