SDA9415-B13 Datasheet, PDF (89/185 Pages) Micronas – Display Processor and Scan Rate Converter

SDA 9415 - B13
Preliminary Data Sheet
((A*)ⁿ,ϒ) - Output signal, field A line-scanning pattern interpolated into field B at time n,
displayed as line-scanning pattern ϒ
(Aⁿ B^n-1,∼+ϒΦ=ϑ=Output signal, frame AB at time n, progressive
The table below describes the different scan rate conversion algorithms and the
corresponding line-scanning pattern sequences. The delay between the input field and
the corresponding output fields depends on the OPDELM parameter and the default
value for the delay is an half input field.
Input fields
Aⁿ
time
A , B ^{Fields available in}
the internal field stores
n-1 n-1
Bⁿ
B^n-1, Aⁿ
Aⁿ, Bⁿ
Output fields
OPDELM lines
c^n-1
Phase 2/0
d^n-1
Phase 3/1
aⁿ
Phase 0
Figure 40 Explanation of operation mode timing
bⁿ
Phase 1
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