SDA9415-B13 Datasheet, PDF (24/185 Pages) Micronas – Display Processor and Scan Rate Converter

SDA 9415 - B13
Preliminary Data Sheet
System description
For this usage the 6 Mbit eDRAM core is separated in two luminance fields and two
chrominance fields (either 4:2:0 or 4:1:1) and a memory area for luminance and
chrominance fields (4:1:1) [maximum circa 1/9 picture] for picture-in-picture applications.
The vector based scan rate conversion is possible for the master channel only.
For the SSC mode the 6 Mbit eDRAM core is split in two 3 Mbit areas, which are able to
contain a maximum of two luminance fields and two chrominance fields (either 4:2:0 or
4:1:1). The figure below shows different applications (“Double window”, “Zoom-in-zoom-
out”). In this case only a simple scan rate conversion (e.g. field doubling for interlaced
conversion: AABB) for both output channels is possible.
Figure 5 Principles of SSC mode
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Micronas