SDA9415-B13 Datasheet, PDF (124/185 Pages) Micronas – Display Processor and Scan Rate Converter

SDA 9415 - B13
Preliminary Data Sheet
’1’, then the store command was sent, but the data aren’t made available yet. If these
bits are ’0’ then the data were made valid and a new write or read cycle can start. The
bits VIMSTATUS, VISSTATUS and OSSTATUS may be checked before writing or
reading new data, otherwise data can be lost by overwriting.
Furthermore the bits NMSTATUS (status of noise measurement: NOISEME) and
LBDSTATUS (status of letter box I²C Bus parameters: SLAA, ELAA, STATUS_SLAA,
STATUS_ELAA, RELY) exist. NMSTATUS signalizes a new value for NOISEME. So if
NMSTATUS is read as ’0’ the current noise measurement has not been updated. If the
NMSTATUS is read as ’1’ a new noise measurement value can be read. LBSTATUS
signalizes at least a change of one of the I²C Bus parameters: SLAA, ELAA,
STATUS_SLAA, STATUS_ELAA, RELY. If the LBDSTATUS is read as ’0’ none of the
I²C Bus parameters has changed its value. If the LBDSTATUS is read as ’1’ at least one
of the I²C Bus parameters has changed its value.
The transmitted data are internally stored in registers. Writing or reading from a not
existing register is permitted and does not generate a fault by the IC.
After switching on the IC (after reset), all bits of the SDA 9415 are set to defined states.
Particularly :
Sub address Default value R/W
Take Sub address Default value R/W
over
Take
over
00
00h
W
VIM 37
48h
W
OS
01
00h
W
VIM 38
9Ch
W
OS
02
00h
W
VIM 39
00h
W
OS
03
00h
W
VIM 3A
00h
W
OS
04
61h
W
VIM 3B
00h
W
OS
05
88h
W
VIM 3C
00h
W
OS
06
00h
W
VIM 3D
00h
W
OS
07
40h
W
VIM 3E
5Ah
W
OS
08
00h
W
VIM 3F
B4h
W
OS
09
00h
W
VIM 40
48h
W
OS
0A
00h
W
VIM 41
90h
W
OS
0B
69h
W
VIM 42
00h
W
OS
0C
00h
W
VIM 43
5Ah
W
OS
0D
90h
W
VIM 44
B4h
W
OS
0E
B4h
W
VIM 45
B0h
W
OS
0F
B4h
W
VIM 46
10h
W
OS
10
90h
W
VIM 47
7Fh
W
OS
11
00h
W
VIM 48
00h
W
OS
12
50h
W
VIM 49
00h
W
OS
124
Micronas