SDA9415-B13 Datasheet, PDF (29/185 Pages) Micronas – Display Processor and Scan Rate Converter

SDA 9415 - B13
Preliminary Data Sheet
System description
internal signal VTSEQM is generated. This signal level is high (VTSEQM=1), if at least
the last to fields were identical. Due to the fixed storage places of the fields in the internal
memory block, this information is necessary for the scan rate conversion processing
("Output sync controller (OSCM/S)" on page 81, it is recommended in case of
VCRMODEM=0 to choose an adaptive operation mode).
The OPDELM I²C Bus parameter is used to adjust the outgoing V-Sync VOUT in relation
to the incoming delayed V-Sync VINM. In case of SSC and MUP mode the
recommended default value should not be changed.
I²C Bus parameter
[Default value]
OPDELM
[170]
Sub address
1Bh
Description
Delay (in number of lines) of the internal V-Sync (delayed
VINM) to the outgoing V-Sync (VOUT)
Table 5
Input write I²C Bus parameter
The internal line counter is used to determine the information about the standard of the
incoming signal.
I²C Bus parameter
TVMODEM
Sub address
7Bh
TVMODES
7Dh
Description
TV standard of the incoming signal master:
1: NTSC
0: PAL
TV standard of the incoming signal slave:
1: NTSC
0: PAL
Table 6
Input read I²C Bus parameter
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