SDA9415-B13 Datasheet, PDF (28/185 Pages) Micronas – Display Processor and Scan Rate Converter

SDA 9415 - B13
Preliminary Data Sheet
System description
CLKM
H1
H2
VINM
Vd
Ffd
(VINDELM * 128 + 1) *
Tclkm
x
Field 1(A)
VINM
Vd
Ffd
Figure 8
(VINDELM * 128 + 1) *
Tclkm
x
Field detection and VINM delay
Field 2(B)
I²C Bus parameter
[Default value]
VINDELM
[0]
VINDELS
[0]
FIEINVM
1 : Field A=1
[0]: Field A=0
FIEINVS
1 : Field A=1
[0]: Field A=0
VCRMODEM
[1]: on
0 : off
VCRMODES
[1]: on
0 : off
Sub address
11h
33h
0Bh
2Dh
0Bh
2Dh
Description
Delay of the incoming V-Sync VINM (must be adjusted
depending on the delay of the HINM signal)
Delay of the incoming V-Sync VINS (must be adjusted
depending on the delay of the HINS signal)
Inversion of the internal field polarity master
Inversion of the internal field polarity slave
In case of non standard interlaced signals (VCR, Play-
Stations) a filtering of the internal field signal has to be done
(should also be used for normal TV signals)
In case of non standard interlaced signals (VCR, Play-
Stations) a filtering of the internal field signal has to be done
(should also be used for normal TV signals)
Table 4
Input write I²C Bus parameter
In case of non-standard signals the field order is indeterminate (e.g. AAA... , BBB... ,
AAABAAAB..., etc.). Therefore a special filtering algorithm is implemented, which can be
switched on by the I²C Bus parameter VCRMODEM/VCRMODES. It is recommended to
set the I²C Bus parameter VCRMODEM=1. In other case (VCRMODEM=0) an additional
28
Micronas