MT40A256M16GE-075EAUT Datasheet, PDF (9/359 Pages) Micron Technology – Automotive DDR4 SDRAM

4Gb: x8, x16 Automotive DDR4 SDRAM
Features
List of Figures
Figure 1: Order Part Number Example .............................................................................................................. 2
Figure 2: 512 Meg x 8 Functional Block Diagram ............................................................................................. 20
Figure 3: 256 Meg x 16 Functional Block Diagram ........................................................................................... 20
Figure 4: 78-Ball x4, x8 Ball Assignments ........................................................................................................ 21
Figure 5: 96-Ball x16 Ball Assignments ............................................................................................................ 22
Figure 6: 78-Ball FBGA – x4, x8 "RH" .............................................................................................................. 26
Figure 7: 96-Ball FBGA – x16 "GE" .................................................................................................................. 27
Figure 8: Simplified State Diagram ................................................................................................................. 28
Figure 9: RESET and Initialization Sequence at Power-On Ramping ................................................................. 34
Figure 10: RESET Procedure at Power Stable Condition ................................................................................... 35
Figure 11: ^tMRD Timing ................................................................................................................................ 37
Figure 12: ^tMOD Timing ................................................................................................................................ 37
Figure 13: DLL-Off Mode Read Timing Operation ........................................................................................... 66
Figure 14: DLL Switch Sequence from DLL-On to DLL-Off .............................................................................. 68
Figure 15: DLL Switch Sequence from DLL-Off to DLL-On .............................................................................. 69
Figure 16: Write Leveling Concept, Example 1 ................................................................................................ 71
Figure 17: Write Leveling Concept, Example 2 ................................................................................................ 72
Figure 18: Write Leveling Sequence (DQS Capturing CK LOW at T1 and CK HIGH at T2) .................................. 73
Figure 19: Write Leveling Exit ......................................................................................................................... 74
Figure 20: CAL Timing Definition ................................................................................................................... 75
Figure 21: CAL Timing Example (Consecutive CS_n = LOW) ............................................................................ 75
Figure 22: CAL Enable Timing – ^tMOD_CAL ................................................................................................... 76
Figure 23: ^tMOD_CAL, MRS to Valid Command Timing with CAL Enabled ....................................................... 76
Figure 24: CAL Enabling MRS to Next MRS Command, ^tMRD_CAL .................................................................. 77
Figure 25: ^tMRD_CAL, Mode Register Cycle Time With CAL Enabled ............................................................... 77
Figure 26: Consecutive READ BL8, CAL3, 1^tCK Preamble, Different Bank Group ............................................... 78
Figure 27: Consecutive READ BL8, CAL4, 1^tCK Preamble, Different Bank Group ............................................... 78
Figure 28: Auto Self Refresh Ranges ................................................................................................................ 81
Figure 29: MPR Block Diagram ....................................................................................................................... 82
Figure 30: MPR READ Timing ........................................................................................................................ 89
Figure 31: MPR Back-to-Back READ Timing ................................................................................................... 89
Figure 32: MPR READ-to-WRITE Timing ........................................................................................................ 90
Figure 33: MPR WRITE and WRITE-to-READ Timing ...................................................................................... 91
Figure 34: MPR Back-to-Back WRITE Timing .................................................................................................. 92
Figure 35: REFRESH Timing ........................................................................................................................... 92
Figure 36: READ-to-REFRESH Timing ............................................................................................................ 93
Figure 37: WRITE-to-REFRESH Timing .......................................................................................................... 93
Figure 38: Clock Mode Change from 1/2 Rate to 1/4 Rate (Initialization) .......................................................... 96
Figure 39: Clock Mode Change After Exiting Self Refresh ................................................................................. 96
Figure 40: Comparison Between Gear-Down Disable and Gear-Down Enable .................................................. 97
Figure 41: Maximum Power-Saving Mode Entry .............................................................................................. 98
Figure 42: Maximum Power-Saving Mode Entry with PDA ............................................................................... 99
Figure 43: Maintaining Maximum Power-Saving Mode with CKE Transition .................................................... 99
Figure 44: Maximum Power-Saving Mode Exit ............................................................................................... 100
Figure 45: Command/Address Parity Operation ............................................................................................. 101
Figure 46: Command/Address Parity During Normal Operation ..................................................................... 103
Figure 47: Persistent CA Parity Error Checking Operation ............................................................................... 104
Figure 48: CA Parity Error Checking – SRE Attempt ........................................................................................ 104
Figure 49: CA Parity Error Checking – SRX Attempt ........................................................................................ 105
Figure 50: CA Parity Error Checking – PDE/PDX ............................................................................................ 105
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b.pdf - Rev. D 01/17 EN
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