MT40A256M16GE-075EAUT Datasheet, PDF (221/359 Pages) Micron Technology – Automotive DDR4 SDRAM

4Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
• If DM_n is sampled HIGH on a given byte lane, the DRAM does not mask the data and
writes this data into the DRAM core.
• If CRC write is enabled, then DM enabled (via MRS) will be selected between write
CRC nonpersistent mode (DM disabled) and write CRC persistent mode (DM ena-
bled).
Figure 166: WRITE Burst Operation, WL = 9 (AL = 0, CWL = 9, BL8)
T0
T1
T2
CK_c
CK_t
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
Command WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Bank Group _BGa
Address
Address
Bank
Col n
DQS_t,
DQS_c
t_WPRE
t_WPST
DQ
DI DI DI DI DI DI DI DI
n n+1 n+2 n+3 n+4 n+5 n+6 n+7
WL = AL + CWL = 9
Time Break
Transitioning Data
Don’t Care
Notes:
1. BL8, WL = 0, AL = 0, CWL = 9, Preamble = 1^tCK.
2. DI n = Data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE command at T0.
5. CA parity = Disable, CS to CA atency = Disable, Read DBI = Disable.
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b.pdf - Rev. D 01/17 EN
221
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