MT40A256M16GE-075EAUT Datasheet, PDF (74/359 Pages) Micron Technology – Automotive DDR4 SDRAM

4Gb: x8, x16 Automotive DDR4 SDRAM
Write Leveling
3. diff_DQS is the differential data strobe. Timing reference points are the zero crossings.
DQS_t is shown with a solid line; DQS_c is shown with a dotted line.
4. CK_t is shown with a solid dark line; CK_c is shown with a dotted line.
5. DQS needs to fulfill minimum pulse width requirements, ^tDQSH (MIN) and ^tDQSL (MIN),
as defined for regular WRITEs; the maximum pulse width is system dependent.
6. ^tWLDQSEN must be satisfied following equation when using ODT:
• DLL = Enable, then ^tWLDQSEN > ^tMOD (MIN) + DODTLon + ^tADC
• DLL = Disable, then ^tWLDQSEN > ^tMOD (MIN) + ^tAONAS
Write Leveling Mode Exit
Write leveling mode should be exited as follows:
1. After the last rising strobe edge (see ~T0), stop driving the strobe signals (see
~Tc0). Note that from this point on, DQ pins are in undefined driving mode and
will remain undefined, until ^tMOD after the respective MR command (Te1).
2. Drive ODT pin LOW (^tIS must be satisfied) and continue registering LOW (see
Tb0).
3. After R_TT is switched off, disable write leveling mode via the MRS command (see
Tc2).
4. After ^tMOD is satisfied (Te1), any valid command can be registered. (MR com-
mands can be issued after ^tMRD [Td1]).
Figure 19: Write Leveling Exit
T0
T1
T2
Ta0
Tb0
Tc0
Tc1
CK_c
CK_t
Command DES
DES
DES
DES
DES
DES
DES
Address
ODT
R_{TT(DQS_t)}
R_{TT(DQS_c)}
DQS_t,
DQS_c
R_TT(DQ)
DQ¹
R_TT(NON)
t_WLO
t_IS
ODTL (OFF)
t_{ADC (MIN)}
t_{ADC (MAX)}
result = 1
Tc2
DES
MR1
Td0
Td1
DES
t_MRD
Valid
Valid
t_MOD
R_TT(Park)
Te0
DES
Te1
Valid
Valid
Undefined Driving Mode
Transitioning
Time Break
Don’t Care
Notes: 1. The DQ result = 1 between Ta0 and Tc0 is a result of the DQS signals capturing CK_t
HIGH just after the T0 state.
2. See previous figure for specific ^tWLO timing.
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b.pdf - Rev. D 01/17 EN
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