MT40A256M16GE-075EAUT Datasheet, PDF (58/359 Pages) Micron Technology – Automotive DDR4 SDRAM

4Gb: x8, x16 Automotive DDR4 SDRAM
Mode Register 5
Table 20: MR5 Register Definition (Continued)
Mode
Register
9
8:6
5
4
3
2:0
Description
CA parity persistent error mode
0 = Disabled
1 = Enabled
Parked ODT value (R_TT(Park))
000 = R_TT(Park) disabled
001 = RZQ/4 (60 ohm)
010 = RZQ/2 (120 ohm)
011 = RZQ/6 (40 ohm)
100 = RZQ/1 (240 ohm)
101 = RZQ/5 (48 ohm)
110 = RZQ/3 (80 ohm)
111 = RZQ/7 (34 ohm)
ODT input buffer for power-down
0 = Buffer enabled
1 = Buffer disabled
CA parity error status
0 = Clear
1 = Error
CRC error status
0 = Clear
1 = Error
CA parity latency mode
000 = Disable
001 = 4 clocks (DDR4-1600/1866/2133)
010 = 5 clocks (DDR4-2400/2666)¹
011 = 6 clocks (DDR4-2933/3200)
100 = 8 clocks (DDR4-2933/3200)
101 = Reserved
110 = Reserved
111 = Reserved
Note: 1. Not allowed when 1/4 rate gear-down mode is enabled.
Data Bus Inversion
The DATA BUS INVERSION (DBI) function has been added to the device and is suppor-
ted only for x8 and x16 configurations (x4 is not supported). The DBI function shares a
common pin with the DM and TDQS functions. The DBI function applies to both READ
and WRITE operations; Write DBI cannot be enabled at the same time the DM function
is enabled. Refer to the TDQS Function Matrix table for valid configurations for all three
functions (TDQS/DM/DBI). DBI is not allowed during MPR READ operation; during an
MPR read, the DRAM ignores the read DBI enable setting in MR5 bit A12. DBI is not al-
lowed during MPR READ operations.
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b.pdf - Rev. D 01/17 EN
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